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The DE3 setup already exists. Along with a version of the custom ADC Front-end daughter cards.
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Ok. I just wanted to throw a couple of ideas out there to see if they were useful.
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Currently, we are upgrading the capability of the entire setup by adding a Stratix V behind 2 DE3s.
Hopefully, in the next iteration, we'll have ADC's with the JEDEC standard. And we'll be able to directly connect a lot of ADCs with one FPGA kit.
Indeed, that would simplify stuff a lot :).
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Given that the ADC data is multiplexed onto a pair of lanes, I suspect there will be enough transitions that you could interface a single lane to the CDR unit of a transceiver. However, I think you'd encounter a lot of problems trying to 'recover' your 6-bits of data out of that data stream, since the frame clock you would use for an LVDS application would not really be available for the transceiver channel (keep in mind that each receiver CDR PLL will have an arbitrary phase shift relative to any of the LVDS receive channels or any PLL locked to the frame clock).
My advice would be to steer clear of the transceiver channels for ADC interfacing. However, you could consider them as communications interfaces for transferring ADC data between boards. For example, ADC-to-DE3 interface via LVDS, and then DE3-to-Stratix V data transport using transceivers (and possibly Stratix V to Stratix V transport via transceivers if needed).
Cheers,
Dave
Honored Contributor
