Honored Contributor
Honored ContributorInteresting. The JEDEC standard is the future and I'd like to see ADCs with them for our application.
But a quick search didn't turn up anything for Ultrasounds that has developed/matured. The AD9250 can be used. The AD9671 is about to be released which could simplify stuff. But I wish it had been released a year ago :). We intend on using the AFE5807 by TI, 8 Channel, 12bit, 80MSps, specifically for Ultrasound applications. And there are 18 ADCs in total. (18 x 8 = 144 Channels) ;) 3 Stratix III boards(DE3 by Terasic) connected to 1 Stratix V (DSP Dev Kit). Each DE3 connected to daughter cards hosting a total of 48 ADC Channels. 48 ADC Channels -- DE3-- 48 ADC Channels -- DE3-- } -- Stratix V Dev kit --> PC (via PCI Express Gen3) 48 ADC Channels -- DE3-- We are kinda limited to the DE3 because it provides a large number of LVDS inputs which we can use to connect to the ADCs. However, the Stratix III on the DE3 isn't powerful enough for processing. And we can't get data off the DE3 to the PC fast enough either. Also, it doesn't have any high-speed transceivers. Hence the above addition of a Stratix V. This isn't a final product, but a research platform. Hence, the large number of channels connected to FPGA development kits. Each aspect of the entire platform has to be configurable for further research into Ultrasonics. I understand your point regarding implementing a subset functionality. And a custom design would easily reduce the number of FPGAs. But as you said, time and resources :). Thanks, Zubair
