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The data is from an ADC for Ultrasound detection at 80MSPS.
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Which part? 80MSps is pretty slow, why are you considering using LVDS? Is this part serializing the data onto a higher data rate LVDS lane? If the part is JEDEC JESD204 compliant, then you can interface it directly to an FPGA transceiver.
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The final bit-stream should be random enough and DC-balanced. but I will run a few tests on actual data just in case.
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It might not be, and unless the ADC is design to take in a modulation source, you cannot use PRBS to 'fix' this part.
It sounds to me like you are trying to re-use existing hardware or a development kit. If that is the case, then just use these kits to get a subset of functionality working, and then design your own board with the actual parts and features you need. That is assuming you have the time and resources to go that route :)
Cheers,
Dave
Honored Contributor
