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AC-coupling seems to be the way to go. I see various strategies. Mostly involving two capacitors. Some indicate a couple of resisters as well. SN65CML100 by TI is also there.
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At 1.6Gbps a couple of 100nF capacitors should be fine.
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I am guessing the speed limits in such a design would be the limitations of the transceivers on the LVDS side. My application requires upwards of 1Gbps. Preferably close to the LVDS limit of the DE3 (1.6Gbps)
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Yes, the limit will be the LVDS.
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The hard-IP transceiver block on the Stratix V in basic mode shouldn't be a choking point at these speeds?
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Worst-case, you may find that 1.6Gbps is too slow (but probably not). If that is the case, then configure the transceiver block receivers and CDR PLLs for 2x or 4x oversampling, and just throw-away the 'extra' bits inside the FPGA. You can also use the 'extra' bits for error checking, eg., in 2x over-sampling mode, confirm that each pair of bits is identical.
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Also, 8/10B introduces a 25% overhead. It should be possible to opt for 64/66B encoding?
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Or PRBS modulation, which introduces no over-head, but does assume a certain level of randomness in your data. Here's a document plus code that generates PRBS patterns:
http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial_src.zip --- Quote Start ---
Sorry for the petty questions. I can clearly see that I need more practical experience on the FPGA than simply musing over it a-lot and thinking over a bigger design.
But I'm learning as it comes. Just don't want to spend time trying to do something impossible :)
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No need to apologize.
Asking intelligent questions that show you've thought about the problem will generally result in useful responses :)
Cheers,
Dave
Honored Contributor
