Using CML or DQS transceiver pins as LVDS possible in Stratix V DSP Dev Kit?

Thank-you.

AC-coupling seems to be the way to go. I see various strategies. Mostly involving two capacitors. Some indicate a couple of resisters as well. SN65CML100 by TI is also there.

I am guessing the speed limits in such a design would be the limitations of the transceivers on the LVDS side. My application requires upwards of 1Gbps. Preferably close to the LVDS limit of the DE3 (1.6Gbps)

The hard-IP transceiver block on the Stratix V in basic mode shouldn't be a choking point at these speeds?

Also, 8/10B introduces a 25% overhead. It should be possible to opt for 64/66B encoding?

Sorry for the petty questions. I can clearly see that I need more practical experience on the FPGA than simply musing over it a-lot and thinking over a bigger design.

But I'm learning as it comes. Just don't want to spend time trying to do something impossible :)

Thank-you,

Zubair