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But what if the frame clock is embedded in the signal itself using a unique pattern.
And the data is encoded for DC balancing..
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Then you can AC couple the LVDS signal to the CML SERDES receiver. You can then use the hard-IP in basic mode, and use it to search for the synchronization patterns.
For example, I use the Stratix IV GX/GT transceivers in basic mode, and send data XOR modulated by a PRBS pattern across an AC-coupled link. Before sending data, I just send the PRBS pattern, and first synchronize lanes to that pattern. I then turn on data and demodulate in the receiving FPGA. The data is disabled periodically to check that the PRBS generators in the TX and RX are still synchronized. 8/10B encoding is nicer, in that its always 'checking'.
Note that the transmitter and receiver should use a common clock reference. The receiver SERDES uses that reference during power-on-initialization, and then will transition to lock-to-data mode (where the data is captured at an optimal location relative to the data eye). The CDR clock and the reference will be 'phase locked', but the phase can change over process-variation-temperature (PVT). The hard-IP FIFOs can be used to cross from the CDR clock domain over to the clock reference domain (or the PLL locked to the clock reference).
Cheers,
Dave
Honored Contributor
