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Altera_Forum
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13 years ago

Using CML or DQS transceiver pins as LVDS possible in Stratix V DSP Dev Kit?

Hi, Forgive me if the question is basic. I am new to the field of FPGAs. I give a short version of the question. And a long version of the question. For those interested :). Note: Re...
Altera_Forum's avatar
Altera_Forum
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13 years ago

General comments to help you (not specific to the Stratix V kit).

LVDS channels and transceiver channels are not interchangeable, so you have to describe your application in a little more detail.

Here's some caveats/typical use-cases.

LVDS channels can operate up to 1Gbps (or so). A multi-channel LVDS interface can consist of multiple data lanes, along with a frame clock. The frame clock is used as a PLL reference, with the PLL increasing the frame clock to the data rate. Depending on the data rate, the clock will be used for single-data-rate or double-data-rate clocking of I/O element registers, or clocking of serializer registers.

A SerDes channel is a stand-alone entity, with the receivers employing clock-and-data-recovery (CDR). If the common-mode voltage of your signal is different than the common-mode of the receiver, then you need to AC couple the signal (you'd have to check whether the LVDS common-mode was in the acceptable range for the Stratix V receivers). Because of the AC coupling, your input data stream needs to be modulated to ensure a zero DC bias, eg., 8/10B encoding, or PRBS modulation. Multi-channel SerDes applications rely on synchronization/alignment codes being sent across the stand-alone channels, so they are not 'synchronous' (each lane needs its own clock-domain crossing FIFO).

You can configure a SerDes channel in a pseudo-synchronous mode, where the receiver PLL is held in lock-to-reference (rather than being allowed to transition to lock-to-data), however, this only works for low frequencies. In this mode, for a mutli-lane application, you would still need to send synchronization codes to align the lanes.

If your LVDS data data rate is synchronous and 'not too high', you may want to consider using external LVDS-to-LVCMOS level translators. National Semiconductor (now owned by Texas Instruments) have some 9-bit parts that operated to ~100Mbps

http://www.ti.com/lit/ds/symlink/ds92lv090a.pdf

Check out the "LVDS Owners Manual"

http://www.ti.com/lit/ml/snla187/snla187.pdf

Cheers,

Dave