Alright.. here you go!!# **************************************************************# Create Clock# **************************************************************
create_clock -period 20 -name clkin_50 [get_ports {clkin_50}]# create_clock -period 8 -name clkin_125 [get_ports {clkin_125}]
create_clock -period 100 -name tck [get_ports {altera_reserved_tck}]
create_clock -period 8 -name virtual_enet_rx_clk_125M
create_clock -period 40 -name virtual_enet_rx_clk_25M
create_clock -period 400 -name virtual_enet_rx_clk_2M5
create_clock -period 8 -name enet_rx_clk_125M [get_ports {enet_rx_clk}]
create_clock -period 40 -name enet_rx_clk_25M [get_ports {enet_rx_clk}] -add
create_clock -period 400 -name enet_rx_clk_2M5 [get_ports {enet_rx_clk}] -add
create_clock -period 40 -name enet_tx_clk_25M [get_ports {enet_tx_clk}]
create_clock -period 400 -name enet_tx_clk_2M5 [get_ports {enet_tx_clk}] -add# **************************************************************# Create Generated Clock# **************************************************************
create_generated_clock -name enet_gtx_clk -source [get_pins {this_stratixIII_3sl150_dev_niosII_standard_sopc|the_sys_pll|the_pll|altpll_component|auto_generated|pll1|clk[1]}] [get_ports {enet_gtx_clk}]# **************************************************************# Set Clock Latency# **************************************************************
# **************************************************************# Set Clock Uncertainty# **************************************************************
# **************************************************************# Set Input Delay# **************************************************************
set_input_delay -clock { virtual_enet_rx_clk_125M } -min 0 [get_ports {enet_rx_col enet_rx_crs enet_rx_d[0] enet_rx_d[1] enet_rx_d[2] enet_rx_d[3] enet_rx_d[4] enet_rx_d[5] enet_rx_d[6] enet_rx_d[7] enet_rx_dv enet_rx_er}]
set_input_delay -clock { virtual_enet_rx_clk_125M } -max -add_delay 6 [get_ports {enet_rx_col enet_rx_crs enet_rx_d[0] enet_rx_d[1] enet_rx_d[2] enet_rx_d[3] enet_rx_d[4] enet_rx_d[5] enet_rx_d[6] enet_rx_d[7] enet_rx_dv enet_rx_er}]
set_input_delay -clock { virtual_enet_rx_clk_25M } -min -add_delay 9.5 [get_ports {enet_rx_col enet_rx_crs enet_rx_d[0] enet_rx_d[1] enet_rx_d[2] enet_rx_d[3] enet_rx_d[4] enet_rx_d[5] enet_rx_d[6] enet_rx_d[7] enet_rx_dv enet_rx_er}]
set_input_delay -clock { virtual_enet_rx_clk_25M } -max -add_delay 30.5 [get_ports {enet_rx_col enet_rx_crs enet_rx_d[0] enet_rx_d[1] enet_rx_d[2] enet_rx_d[3] enet_rx_d[4] enet_rx_d[5] enet_rx_d[6] enet_rx_d[7] enet_rx_dv enet_rx_er}]
set_input_delay -clock { virtual_enet_rx_clk_2M5 } -min -add_delay 9.5 [get_ports {enet_rx_col enet_rx_crs enet_rx_d[0] enet_rx_d[1] enet_rx_d[2] enet_rx_d[3] enet_rx_d[4] enet_rx_d[5] enet_rx_d[6] enet_rx_d[7] enet_rx_dv enet_rx_er}]
set_input_delay -clock { virtual_enet_rx_clk_2M5 } -max -add_delay 390.5 [get_ports {enet_rx_col enet_rx_crs enet_rx_d[0] enet_rx_d[1] enet_rx_d[2] enet_rx_d[3] enet_rx_d[4] enet_rx_d[5] enet_rx_d[6] enet_rx_d[7] enet_rx_dv enet_rx_er}]
# **************************************************************# Set Output Delay# **************************************************************
set_output_delay -clock { enet_gtx_clk } -min -0.5 [get_ports {enet_tx_d[0] enet_tx_d[1] enet_tx_d[2] enet_tx_d[3] enet_tx_d[4] enet_tx_d[5] enet_tx_d[6] enet_tx_d[7] enet_tx_en enet_tx_er}]
set_output_delay -clock { enet_gtx_clk } -max -add_delay 2.5 [get_ports {enet_tx_d[0] enet_tx_d[1] enet_tx_d[2] enet_tx_d[3] enet_tx_d[4] enet_tx_d[5] enet_tx_d[6] enet_tx_d[7] enet_tx_en enet_tx_er}]
set_output_delay -clock { enet_tx_clk_25M } -min -add_delay -1.5 [get_ports {enet_tx_d[0] enet_tx_d[1] enet_tx_d[2] enet_tx_d[3] enet_tx_d[4] enet_tx_d[5] enet_tx_d[6] enet_tx_d[7] enet_tx_en enet_tx_er}]
set_output_delay -clock { enet_tx_clk_25M } -max -add_delay 9.5 [get_ports {enet_tx_d[0] enet_tx_d[1] enet_tx_d[2] enet_tx_d[3] enet_tx_d[4] enet_tx_d[5] enet_tx_d[6] enet_tx_d[7] enet_tx_en enet_tx_er}]
set_output_delay -clock { enet_tx_clk_2M5 } -min -add_delay -1.5 [get_ports {enet_tx_d[0] enet_tx_d[1] enet_tx_d[2] enet_tx_d[3] enet_tx_d[4] enet_tx_d[5] enet_tx_d[6] enet_tx_d[7] enet_tx_en enet_tx_er}]
set_output_delay -clock { enet_tx_clk_2M5 } -max -add_delay 9.5 [get_ports {enet_tx_d[0] enet_tx_d[1] enet_tx_d[2] enet_tx_d[3] enet_tx_d[4] enet_tx_d[5] enet_tx_d[6] enet_tx_d[7] enet_tx_en enet_tx_er}]
# **************************************************************# Set Clock Groups# **************************************************************
set_clock_groups -exclusive -group this_stratixIII_3sl150_dev_niosII_standard_sopc|the_altmemddr|altmemddr_controller_phy_inst|alt_mem_phy_inst|altmemddr_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]
set_clock_groups -exclusive -group this_stratixIII_3sl150_dev_niosII_standard_sopc|the_sys_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]
set_clock_groups -exclusive -group clkin_50# set_clock_groups -exclusive -group clkin_125# set_clock_groups -exclusive -group tck
set_clock_groups -exclusive -group [get_clocks {virtual_enet_rx_clk_125M enet_rx_clk_125M enet_gtx_clk}] -group [get_clocks {virtual_enet_rx_clk_25M enet_rx_clk_25M enet_tx_clk_25M}] -group [get_clocks {virtual_enet_rx_clk_2M5 enet_rx_clk_2M5 enet_tx_clk_2M5}]
# **************************************************************# Set False Path# **************************************************************
set_false_path -from [get_clocks {this_stratixIII_3sl150_dev_niosII_standard_sopc|the_sys_pll|the_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {enet_tx_clk_2M5}]
set_false_path -from [get_clocks {enet_tx_clk_2M5}] -to [get_clocks {this_stratixIII_3sl150_dev_niosII_standard_sopc|the_sys_pll|the_pll|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {this_stratixIII_3sl150_dev_niosII_standard_sopc|the_sys_pll|the_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {enet_tx_clk_25M}]
set_false_path -from [get_clocks {enet_tx_clk_25M}] -to [get_clocks {this_stratixIII_3sl150_dev_niosII_standard_sopc|the_sys_pll|the_pll|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {virtual_enet_rx_clk_125M virtual_enet_rx_clk_25M virtual_enet_rx_clk_2M5}] -to [get_clocks {this_stratixIII_3sl150_dev_niosII_standard_sopc|the_sys_pll|the_pll|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {this_stratixIII_3sl150_dev_niosII_standard_sopc|the_sys_pll|the_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {enet_rx_clk_2M5 enet_rx_clk_25M enet_rx_clk_125M}]
set_false_path -from [get_clocks {virtual_enet_rx_clk_25M}] -to [get_clocks {enet_tx_clk_25M}]
set_false_path -from [get_clocks {virtual_enet_rx_clk_2M5}] -to [get_clocks {enet_tx_clk_2M5}]
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