Forum Discussion
Mingyuexin
Occasional Contributor
Occasional ContributorTiming violation when route emac from HPS to FPGA in quartus prime standard 18.1
Hi, I need to use route EMAC from HPS to FPGA because our system need 4 channels of ethernets, and one USB interface also. I refer to the examples from here https://rocketboards.org/foswiki/Projec...
KennyT_altera
Super Contributor
Super ContributorI just found this document. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_handbook.pdf
page 183 although this is A10, It should be apply to all device.
Basically, it mention that you need a different IO standards if your frequencies running too high.
MingyuexinOccasional Contributor
Occasional ContributorHi,
Thank you very much for the answer again.
The RGMII runs at 125 MHz, it's not very high speed.
I have given up to implement RGMII in this design now.
Anyway, thank you very much for the information.
With best wishes
Jasmine
