Timing violation when route emac from HPS to FPGA in quartus prime standard 18.1

As I said, this path has both setup violation and hold violation. Please advice me how to over constrain this path. I attached the detail of this path. I referred to http://www.rkra.de/quartus/Timequest/Timing%20Constraints%20-%20Altera%20Wiki.html for over constrain advice, as I know, over constrain works for small setup violation, and there is long distance between two registers. But in my case, I do not see two registers.

With best wishes

Jasmine