Forum Discussion
Mingyuexin
Occasional Contributor
Occasional ContributorTiming violation when route emac from HPS to FPGA in quartus prime standard 18.1
Hi, I need to use route EMAC from HPS to FPGA because our system need 4 channels of ethernets, and one USB interface also. I refer to the examples from here https://rocketboards.org/foswiki/Projec...
KennyT_altera
Super Contributor
Super Contributorcan u attached your screenshot? the problem is that I don't see this clock TX_CLK_OUT_2_5 being shown in the timing report
U can check all the sdc written session
MingyuexinHi,
See the attachment, TX_CLK_OUT_2_5 is at item 35.
With best wishes
Jasmine
- Mingyuexin
This is the snapshot that is missing in the previous reply.
With best wishes
Jasmine
