Forum Discussion
FawazJ_Altera
Frequent Contributor
7 years agoHello,
The best approach to sync data in this case would be the On chip FIFO with dual clock support.
In this IP, you can set 2 different clocks for data in and data out, with the flexibility of setting the FIFO depth.
Furthermore, if you can export a clock signal from this processor, you can feed it to a PLL, and this PLL will feed the FPGA. Also, you can do it in reverse, if this processor accepts external clock signal, you can use FPGA PLL to feed both FPGA design and external processor.
Thanks