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NAika's avatar
NAika
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7 years ago
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Structure of Cyclone Ⅴ and EPCQ-A

I am trying to realize the Cyclone V configuration using EPCQ-A(AS Mode). EPCQ-A Output Delay(tCLQX) min 1.5ns Cyclone V Input hold time(tDH) min 2.9ns Could you tell me what kind of connectio...
Nooraini_Y_Intel's avatar
Nooraini_Y_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi NAika,

You can follow the guideline under chapter “1.4 Evaluating Data Setup and Hold Timing Slack” in AN822 to evaluate the data hold time slack on your board in order to ensure you are meeting the Cyclone V data hold time (tDH) requirement.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an822.pdf

Also, you can refer to the following KDB for other recommendation that you can consider for Cyclone V AS configuration board design:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/component/2018/why-does-cyclone-v-as-configuration-with-epcq-epcqa-devices-fail.html

Regards,

Nooraini