Forum Discussion
New ContributorStructure of Cyclone Ⅴ and EPCQ-A
Hi NAika,
You can follow the guideline under chapter “1.4 Evaluating Data Setup and Hold Timing Slack” in AN822 to evaluate the data hold time slack on your board in order to ensure you are meeting the Cyclone V data hold time (tDH) requirement.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an822.pdf
Also, you can refer to the following KDB for other recommendation that you can consider for Cyclone V AS configuration board design:
Regards,
Nooraini
ContributorGood spot. I think the datasheet for the EPCQ device is misleading. I think the problem is that Intel/Altera always capture the figures from the FPGA's point of view - if that makes sense (I'm not sure it does...)
Refer to figure 53 (page 95) of the equivalent Micron part. All timings, and in particular t_CLQV & t_CLQX are with respect to the rising edge of the clock:
Given data is latched into the FPGA on the falling edge of DCLK I think perhaps Intel/Altera have tried to reference the same edge in the memory device's datasheet when, I suspect, they're no different to the Micron (or other 3rd party) devices.
Cheers,
Alex
