Stratix V DSP Kit Transcievers

Hi,

I was looking at the schematic and the reference manual for the Stratix V DSP development kit

http://www.altera.com/products/devkits/altera/kit-stratix-v-dsp.html

The transceivers are on Bank 1 of the HSMC ports A and B.

What I don't understand is why there are single-ended clock input/outputs on the banks of the port for transceivers.

Am I missing something? Can transceivers function easily without a differential frame clock?

I have a differential frame clock I'd like to use to simplify the of deciphering the data-stream.

But I can't connect it to the Transceiver PHY mega-function's CDR reference clock.

And connecting the single-ended clock to the CDR reference clock of the mega-function isn't working either.

Any ideas as to where I am going wrong?

Thanks

Zubair