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What I don't understand is why there are single-ended clock input/outputs on the banks of the port for transceivers.
Am I missing something?
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The HSMC standard does not define clocks for the transceivers. The connector defines clocks, but says nothing about what they need to go to. Ideally there would be a clock going to a transceiver block REFCLK input, but that is not a requirement.
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Can transceivers function easily without a differential frame clock?
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The term "frame clock" is terminology used to describe a lower-speed clock that is synchronous, i.e., has some form of time alignment, with LVDS data.
A transceiver has a REFCLK, which is a reference clock with a relationship to the bit-rate of the transceiver data, but no requirements on a phase relationship (other than being low jitter).
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I have a differential frame clock I'd like to use to simplify the of deciphering the data-stream.
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That'll never happen. The receiver CDRs lock their own PLLs. You cannot recover multi-bit-width data unless the data stream itself has some form of synchronizing code embedded within it.
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But I can't connect it to the Transceiver PHY mega-function's CDR reference clock.
And connecting the single-ended clock to the CDR reference clock of the mega-function isn't working either.
Any ideas as to where I am going wrong?
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Check out the example designs that come with the kit. Perhaps they have a clocking scheme example you can re-use.
What are you trying to do?
Cheers,
Dave
Honored Contributor
