Stratix 10 SoC Dev Kit - L-tile - FPGA-DDR4 (SODIMM ) Example design

Hi,

Yes, I have downloaded the package & tried to create the project as mentioned in the readme file.

I ran the below command in command prompt & I am getting the error message while creating the project

quartus_sh -t make_qii_design.tcl

------------------------------------------------------------------------------------------------

Error (23035): Tcl error: child process exited abnormally
while executing
"exec -ignorestderr $qsys_generate_exe_path $qsys_file --pro --synthesis --family=$family --part=$device >>& ip_generate.out"
(file "make_qii_design.tcl" line 98)
------------------------------------------------
child process exited abnormally
while executing
"exec -ignorestderr $qsys_generate_exe_path $qsys_file --pro --synthesis --family=$family --part=$device >>& ip_generate.out"
(file "make_qii_design.tcl" line 98)
------------------------------------------------
Error (23031): Evaluation of Tcl script make_qii_design.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 2 errors, 0 warnings
Error: Peak virtual memory: 4871 megabytes
Error: Processing ended: Tue Aug 25 09:59:37 2020
Error: Elapsed time: 00:00:23

------------------------------------------------------------------------------------------

I am using Quartus pro 18.1 & licensed for stratix 10 device.

With regards,

HPB