Storing bitstream in Startix V GS SI eval kit and transmitting through the transmitter.

Hi Srikanth,

As I understand it, you have some inquiries related to using the SV GS SI eval kit. It would be great if you could further elaborate on the specific application that you are targeting. For example, if you are trying to use transceiver or GPIO, what is the data rate that you are using, what is the protocol to be comply and etc.

Just to set a correct expectation. Generally we would address specific inquiry related to FPGA but not design implementation. However, I will try my best to assist to my best knowledge.

If you are using transceiver in your design, you can start with simple Native PHY design + TX PLL + reset controller and send fix data pattern through Native PHY TX. It is recommended for you to perform a Modelsim simulation prior to hardware testing to help isolating any functional related problem.

Please let me know if there is any concern. Thank you.