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MamaSaru's avatar
MamaSaru
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

SLVS signal pin feeding Deserializer

Hi, I can’t find Intel FPGA device like below: Can receive 1.6Gbps SLVS differential signals. These SLVS inputs feed each source synchronous Deserializer. Number of SLVS inputs is 60 pair, prefe...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago
Hi Masaru, Apologize that the SLVS I/O standard is only available in MAX 10. For Arria 10 and Cyclone 10 GX, you might need to choose the different pair in which the electrical specification is matching the input SLVS signal. Regards, YL