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JET60200's avatar
JET60200
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5 years ago

Slack violation of "pcie_a10_hip|~CORE_CLK_OUT"

Hello , On A10SOC KIT board, I compile PCIe_gen3x8-Avmm design example, but Time Report show below critical warning ？ I wanto understand what‘s this Critical Warning meaning’ is ? Does it ...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

Yes, it should not be allowed. This happened usually you use a different version of Quartus Prime.


This clock used for signal tap. What you can try is use different seeds to close the timing since the value is small.