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Sushmita's avatar
Sushmita
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Should read request signal in avalon interface be a continously high signal or just a pulse?

Hi, I want to use avalon interface to read the data from DDR to BRAM with a burst size of 512, bit interface is 64. Currently i am sending the read request as a pulse. But i am not sure if it is the...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

When the slave asserts waitrequest, the transfer is delayed. While waitrequest is asserted, the address and other control signals are held constant. Transfers complete on the rising edge of the first clk after the slave interface deasserts waitrequest.