New Contributor
New ContributorCan you, please, explain in the follwing code of yours the following issues:
1. What should I do to for "write operation needs 3 cycle".
2. "hold nconfig min 250ns, 4 cycle at 12 MHz" isn't that an automatic command and I'm unable to change the number of cycles?
3."elsif(cnt > 60000000) then" has no continuation and also "db_avalon_write" remains at '1' for good?
ContributorFirst you should know that I gather this timing informations from Intel's configuration user guide (https://www.intel.com/content/www/us/en/docs/programmable/683865/current/fpga-configuration-overview.html) and flash memory user guide (https://www.intel.com/content/www/us/en/docs/programmable/683180/18-0/user-flash-memory-overview.html). You should read them. Your cycle needs will change if your clock is different. After that:
1.Actually you just wait for 3 cycle for "write operation". I did this with using counter. Counter increases every clock cycle. So in 3. cycle it has been waited for 3 cycle = 250ns at 12MHz.
2.As I said you calculate the cycles recpect to your clock cycle. The important thing is the time (250ns) not the cycle count. And it is not an automatic command you drive the bits. If you clear the bits earlier, you may be dont get what you want.
3.Yes it has no continuation because 250ns after the writing the reconfig bits, the device must be restart itself. So I wait here until device restart itself and hold it for 60000000 cycles just for guarantee the operation. So you can change it at least min 250ns.
New ContributorI found in the datasheet the parameter the table of parameters:
I assume that this is the source for the figure 250nS. So, since I'm using 25Mhz CLK I need to change the cnt= 3 to cnt = 7 for db_avalon_write <= '0';
The condition cnt > 60000000 fits to a time of 60,000,000/12.6e6 =4.76 Sec.
The only figure I can find is in the following table:
Do you any insights about this issue?
New ContributorIn AN741:
Which complies with the UG-MAX10-Configuration
In your code :
The signal boot_cfm_sel should be assigned to writdata(1) and writdata(0) should be set to '1' in order to ignore the physical
config_sel pin and setting the loading image according to boot_cfm_sel.
ContributorLast counter value is not important. It is just waiting for restarting the device. You can change it. And AN741 is not complies with UG-MAX10-Configuration. In AN741 they assign reg 1 to 0x3 that means overwrite selected and Image 1 will be used.
Also sorry, I made a mistake on that code. Here is the revised rsu_reconfig function:
when rsu_reconfig => u_valid_in <= '0'; onchip_flash_csr_write <= '0'; if(cnt = 0) then db_avalon_address <= "001"; db_avalon_writedata(0) <= '1'; -- set config_sel_overwrite db_avalon_writedata(1) <= boot_cfm_sel; -- set config_sel db_avalon_writedata(31 downto 2) <= (others => '0'); -- reserved db_avalon_write <= '1'; db_avalon_read <= '0'; cnt <= cnt + 1; elsif(cnt = 3) then -- write operation needs 3 cycle db_avalon_write <= '0'; db_avalon_read <= '0'; cnt <= cnt + 1; elsif(cnt = 4) then db_avalon_address <= "011"; -- busy reg db_avalon_read <= '1'; db_avalon_write <= '0'; cnt <= cnt + 1; elsif(cnt = 5) then -- read operation needs 1 cycle db_avalon_read <= '0'; db_avalon_write <= '0'; cnt <= cnt + 1; elsif(cnt = 6) then -- read data came in 2th cycle if(db_avalon_readdata /= x"00000000") then -- if ufm/cfm busy cnt <= 4; -- go back until busy flag is over else cnt <= cnt + 1; end if; elsif(cnt = 250000000) then -- high cnt value because of CPU should read the RSU checksum acknowledge db_avalon_address <= "000"; -- trigger reconfig db_avalon_writedata <= x"00000001"; -- hold nconfig min 250ns, 4 cycle at 12 MHz db_avalon_write <= '1'; db_avalon_read <= '0'; cnt <= cnt + 1; else -- wait for FPGA trig reconfig cnt <= cnt + 1; end if;
