Forum Discussion

alex2021's avatar
alex2021
Icon for New Contributor rankNew Contributor
5 years ago

Problem running altera_pcie example designs simulation

Problem running Intel Quartus FPGA example test case in: altera_pcie/altera_pcie_cv_hip_avmm/example_designs/ep_g2x4.qsys I got this error message when running simv: Warning-[STASKW_CO] Cann...
alex2021's avatar
alex2021
Icon for New Contributor rankNew Contributor
5 years ago

The path works even with double //.

I already found the cause. There was a mistake in Generate/Testbench for ep_g2x4. The top module used was "control", not "ep_g2x4_tb". The problem went away after I correct it to use ep_g2x4_tb.