Problem Implementing clock in Cyclone II (Altera-DE2)

Hi,

because it is Christmas. A simple clock divider you simply need to change the divider variable to the correct number. It depends from your ref clock and what clock you want. Alternatively, you can use a PLL using the megawizzard.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY counter IS
	PORT(
		CLK		: IN 		STD_LOGIC;
		CLR		: IN 		STD_LOGIC;
		DIV_CLK	: OUT 	STD_LOGIC
	);
END ENTITY counter;
ARCHITECTURE logic OF counter IS
	BEGIN
	
		PROCESS(CLK, CLR)
		VARIABLE DIVIDER : UNSIGNED(23 DOWNTO 0) := (OTHERS => '0');
		
		BEGIN
		
			IF CLR = '0' THEN
				DIVIDER := (OTHERS => '0');
			ELSIF rising_edge(CLK) THEN
				DIVIDER := DIVIDER + 1;
			
				IF DIVIDER = "011111111101001000000000" THEN
					
					DIVIDER := (OTHERS => '0');
					DIV_CLK <= '1';
					
				ELSE
						
					DIV_CLK <= '0';
						
				END IF;
			END IF;
		END PROCESS;
	
END ARCHITECTURE logic;