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zhangyi17's avatar
zhangyi17
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7 years ago

Problem following I2C Remote System Upgrade Example (Max 10)

Hello Everybody. I am an old timer from the Altera Forum. First timer posted on the Intel Forum. I've been trying to follow the I2C Remote System Upgrade Example (Max 10) for a week now (see attach...
zhangyi17's avatar
zhangyi17
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7 years ago

I dig a little bit deeper by going into the Qsys Nios II processor..I don't see any port been exported for UART

and the top level design doesn't have any UART port either

Could this be the problem? Anyone??

  • Ahmed_H_Intel1's avatar
    Ahmed_H_Intel1
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    7 years ago

    You don't have to. BTW I see you are connecting the Jtag UART to instruction master (just connect to the Data Master of NIOS II)

    • zhangyi17's avatar
      zhangyi17
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      7 years ago

      The user guide (attached) for this lab explicitly connected a PC with COM port to the UART port on the Eval board via a USB/UART converter.

      In the qsys design, there is no UART at all.

      How is this suppose to work then?

    • Ahmed_H_Intel1's avatar
      Ahmed_H_Intel1
      Icon for Frequent Contributor rankFrequent Contributor
      7 years ago

      There is a UART in Qsys (Master), in the slave you don't have to have a UART, you need only to download the SOF file to it and will be waiting the commands come from the master boards.

      You need to connect the slave board to a PC just to download the .sof file.