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Honored Contributor
Honored ContributorPLL on Altera DE3 Development Board doenst work
Hello everyone, im using the developement board altera DE3 (Stratix III , EP3SL150f1152C2N) for my master thesis. Im trying to use a PLL to get a higher clock. Therefor im using the internal 50...
Altera_ForumHonored Contributor
Honored ContributorIt appears the physical PLL signal are not properly connected inside your PLL component (ie. clk => open).
I don't understand why you used Qsys to generate the PLL component which is supposed to be controlled like an Avalon MM slave: from the code you posted it seems your design doesn't rely on an Avalon infrastructure.
