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Pa1_bhandari's avatar
Pa1_bhandari
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6 years ago

PCIE hard ip issue, when i try to integrate two PCIE hard IP's ,than synthesis is being failed.( family Cyclone V , gx )

Hi i'am initially making pin assignment in cyclone v , when i try to build an top module (with just pin's) and try to synthesize with few modules its getting compiled and synthesized, but when i add ...
Nathan_R_Intel's avatar
Nathan_R_Intel
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6 years ago
Hie, Could you please provide your design achieve (.qar) so I can check what is causing the issue. Current;ly, your channel placement is correct. I need information how is the IP components connected in the design to understand the failure. Regards, Nathan