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Pa1_bhandari's avatar
Pa1_bhandari
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6 years ago

PCIE hard ip issue, when i try to integrate two PCIE hard IP's ,than synthesis is being failed.( family Cyclone V , gx )

Hi i'am initially making pin assignment in cyclone v , when i try to build an top module (with just pin's) and try to synthesize with few modules its getting compiled and synthesized, but when i add ...
Nathan_R_Intel's avatar
Nathan_R_Intel
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6 years ago
Hie, Please check my replies to your questions: Question: 1.1.We are planning to use X1 and X2 for two PCIe Endpoints. Answer: Yes this can be supported. However, you need to place the x1 and x2 in different PCIe Hard IP (HIP). You will need to use both the PCIe Hard IP (HIP) available in your device. Please refer to Table 4-2 in handbook to determine if your device supports both x1 and x2 configuration. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v3.pdf Question: 2.Can we generate a IP with x2 lane support and instantiate them and keep the one of the lane unused . Answer: Yes you may. If only a x1 is connected on the other end, the PCIe link will down-configure and run x1. Question: 3. Following are the pin assignments we are planning to use . Answer: The pin assignment seems correct. You are using the upper HIP. However, please get Quartus Prime to complete compilation to 100% be certain the channel placement is correct. As I explained above certain configurations is not supported in the upper/lower HIP based on device. Question: When we try the above step we are getting the compilation error as below Answer: It seems you are not following the channel placement guideline; thus resulting the reported erros. Hence, please refer to "PCIe Supported Configurations and Placement Guidelines" in Pg 4-7 (Pg 116/171) in : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v3.pdf Regards, Nathan
  • Pa1_bhandari's avatar
    Pa1_bhandari
    Icon for New Contributor rankNew Contributor
    6 years ago

    Dear Nathan,

    Thank you so much for your valuable time and links, i will check them, if i get doubt's i will let you know.

    Best Regard's

    Pavan

    • Pa1_bhandari's avatar
      Pa1_bhandari
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      6 years ago

      @lakshmi.narayanan@blackpeppertech.com @vedashri.parashivamurthy@blackpeppertech.com

      Hi Nathan,

      As i have assigned top(EP1) with x1 lane and bottom(EP0) with x2 lane.

      currently there is no design , only top file with I/O's.

      Bank Number | Location |

      —————————————————————

      EP1

      GXB_L2 GXB_TX_L6n P3 PCIE _EP1_TX[0]_N

      GXB_L2 GXB_TX_L6p P4 PCIE _EP1_TX[0]_P

      GXB_L2 GXB_Rx_L6n R1 PCIE _EP1_RX[0]_N

      GXB_L2 GXB_RX_L6p R2 PCIE _EP1_RX[0_P

      GXB_L2 REFCLK2Lp P8 PCIE _EP1_REFCLK_N

      GXB_L2 REFCLK2Ln N7 PCIE _EP1_REFCLK_P

      EP0

      GXB_TX_L1n AD3 PCI_EP0_TX_N[1]

      GXB_TX_L1p AD4 PCI_EP0_TX_P[1]

      GXB_RX_L1p,GXB_REFCLK_L1p AE2 PCI_EP0_RX_N[1]

      GXB_RX_L1n,GXB_REFCLK_L1n AE1 PCI_EP0_RX_P[1]

      GXB_TX_L0p AF4 PCI_EP0_TX_P[1]

      GXB_TX_L0n AF3 PCI_EP0_TX_N[0]

      GXB_RX_L0p,GXB_REFCLK_L0p AG2 PCI_EP0_RX_N[0]

      GXB_RX_L0n,GXB_REFCLK_L0n AG1 PCI_EP0_RX_P[0]

      REFCLK0Lp W8 PCI_EP0_REFCLK_P

      REFCLK0Ln W7 PCI_EP0_REFCLK_N

      Error (177035): The input pin PCI_EP0_RX_N[0] assigned to HSSI Pin_AG1 has no fanout.

      Error (177035): The input pin PCI_EP0_RX_N[1] assigned to HSSI Pin_AE1 has no fanout.

      Error (177035): The input pin PCI_EP1_REFCLK_P assigned to HSSI Pin_N7 has no fanout.

      Error (177035): The input pin PCI_EP1_REFCLK_N assigned to HSSI Pin_P8 has no fanout.

      Error (177035): The input pin PCI_EP1_RX_P[0] assigned to HSSI Pin_R2 has no fanout.

      Error (177035): The input pin PCI_EP1_RX_N[0] assigned to HSSI Pin_R1 has no fanout.

      Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device.

      Thanks and Regards

      Pavan