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Pa1_bhandari's avatar
Pa1_bhandari
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6 years ago

PCIE hard ip issue, when i try to integrate two PCIE hard IP's ,than synthesis is being failed.( family Cyclone V , gx )

Hi i'am initially making pin assignment in cyclone v , when i try to build an top module (with just pin's) and try to synthesize with few modules its getting compiled and synthesized, but when i add ...
Pa1_bhandari's avatar
Pa1_bhandari
Icon for New Contributor rankNew Contributor
6 years ago

Dear Nathan,

Many thank's for the link's which you have sent.

Actually We are in the initial stage of project were we need to share ".pin" file to Board team.

When we try to do assignment with early pin planning for PCIE we are facing the issue related to compilation .

When we assign other pins we don't have issue.

Can you help us on this ?

Thanks and regards

Pavan Kumar