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Pa1_bhandari's avatar
Pa1_bhandari
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6 years ago

PCIE hard ip issue, when i try to integrate two PCIE hard IP's ,than synthesis is being failed.( family Cyclone V , gx )

Hi i'am initially making pin assignment in cyclone v , when i try to build an top module (with just pin's) and try to synthesize with few modules its getting compiled and synthesized, but when i add ...
Nathan_R_Intel's avatar
Nathan_R_Intel
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6 years ago
Hie, You can try using the example design in the following links as a reference to build your design: https://fpgawiki.intel.com/wiki/Reference_Design:_Gen2x4_AVMM_DMA_-_Cyclone_V Also, please refer to our user guide on how to build the PCIe reference design for Cyclone V. The links for the user guide are below: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_c5_pcie_avst.pdf https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_c5_pcie_avmm.pdf Regards, Nathan