fpgaBeginner
New Contributor
New ContributorOn my fpga, 'or' is 'and' and vice versa
Hello, I recently bought an ALTERA Cyclone IV EP4CE6 FPGA and tried to create the first project. When key_1 and key_2 were clamped, led_1 should have been lit.
But led_1 is lit when key_1 is clamped when key_2 is not pressed.
library IEEE; use IEEE.STD_LOGIC_1164.all;
entity led_test is
port(key_1, key_2: in STD_LOGIC;
led_1: out STD_LOGIC);
end;
architecture synth of led_test is
begin
led_1 <= key_1 and key_2;
end;
if I write led_1 <= key_1 or key_2; then all led_1 lights up only when both buttons (key_1 and key_2) are pressed, if only one of them is pressed, then led_1 does not light
What am I doing wrong? Could this be a problem with the fpga?
