Honored Contributor
Honored ContributorIf you created a new hardware project then chances are your device options "unused I/O" are set to ground. There is an active low signal on that board that notifies the CPLD to send a new FPGA hardware image. So what might be happening is you download your design, that reconfig pin is unused and pulled low as a result, the then CPLD loads an image out of flash and sends that to the FPGA wiping out your original image. This happens very fast and makes it appear that your design isn't doing anything (I've done this a couple of times....:) ). To fix this try one of the following:
1) Find the pin and pull it high in your design (the pin has a name similar to "reconfig_n") 2) Go into the device options and under the unused I/O set them to "input tri-state". There is a pull-up on that signal so doing this will make sure it stays high. I hope that helps
