Forum Discussion
Hi
Which is actual issue you are facing in your design? Would you mind to share a sample design that is causing the issue? It looks like your design is having assignment issue between LVDS and IOPLL. But we have to look into the design for detail understanding.
Thanks.
Eng Wei
- TRAN_HIEU_0074 years ago
Occasional Contributor
When I use another connection port to connect with IP core TSE, the above error is encountered in the fitter (if I edit in pin planer). But when I edit the port in the Assignments editor The above error does not appear. But project simple_socket_sever not working and stop when I try to debug config pcs. I used the project in the sample. I can not attach files. I don't know why I got this error. InterNiche Portable TCP/IP, v3.1 Copyright 1996-2008 by InterNiche Technologies. All rights reserved. altera_eth_tse_init 0 prep_tse_mac 0 Can't read the MAC address from your board. We will assign you a MAC address. Please enter your 9-digit serial number. This is printed on a label under your Nios dev. board. The first 3 digits of the label are ASJ and the serial number follows this. -->Created "Inet main" task (Prio: 2) Created "clock tick" task (Prio: 3) 123456789 123456789 Your Ethernet MAC address is 00:07:ed:ff:cd:15 prepped 1 interface, initializing... tse_mac_init 0 List of PHY profiles supported (Total profiles = 5)... Profile No. 0 : PHY Name : Marvell 88E1111 PHY OUI : 0x005043 PHY Model Num. : 0x0c PHY Rev. Num. : 0x02 Status Register : 0x11 Speed Bit : 14 Duplex Bit : 13 Link Bit : 10 Profile No. 1 : PHY Name : Marvell Quad PHY 88E1145 PHY OUI : 0x005043 PHY Model Num. : 0x0d PHY Rev. Num. : 0x02 Status Register : 0x11 Speed Bit : 14 Duplex Bit : 13 Link Bit : 10 Profile No. 2 : PHY Name : National DP83865 PHY OUI : 0x080017 PHY Model Num. : 0x07 PHY Rev. Num. : 0x0a Status Register : 0x11 Speed Bit : 3 Duplex Bit : 1 Link Bit : 2 Profile No. 3 : PHY Name : National DP83848C PHY OUI : 0x080017 PHY Model Num. : 0x09 PHY Rev. Num. : 0x00 Status Register : 0x00 Speed Bit : 0 Duplex Bit : 0 Link Bit : 0 Profile No. 4 : PHY Name : Intel PEF7071 PHY OUI : 0x355969 PHY Model Num. : 0x00 PHY Rev. Num. : 0x01 Status Register : 0x00 Speed Bit : 0 Duplex Bit : 0 Link Bit : 0 INFO : TSE MAC 0 found at address 0x10020000 INFO : Multi Channel = No INFO : MDIO Shared = No INFO : MAC Type = 10/100/1000 Ethernet MAC INFO : PCS Enable = Yes INFO : PCS SGMII Enable = Yes INFO : MAC Address = 0x10020000 INFO : MAC Device = tse_mac_device[0] INFO : PHY Marvell 88E1111 found at PHY address 0x00 of MAC Group[0] INFO : PHY OUI = 0x005043 INFO : PHY Model Number = 0x0c INFO : PHY Revision Number = 0x2 INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0] INFO : PHY[0.0] - Advertisement of 1000 Base-T Full Duplex set to 1 INFO : PHY[0.0] - Advertisement of 1000 Base-T Half Duplex set to 1 INFO : PHY[0.0] - Advertisement of 100 Base-T4 set to 0 INFO : PHY[0.0] - Advertisement of 100 Base-TX Full Duplex set to 1 INFO : PHY[0.0] - Advertisement of 100 Base-TX Half Duplex set to 1 INFO : PHY[0.0] - Advertisement of 10 Base-TX Full Duplex set to 1 INFO : PHY[0.0] - Advertisement of 10 Base-TX Half Duplex set to 1 INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... INFO : PHY[0.0] - Auto-Negotiation PASSED -- Program stop here. - TRAN_HIEU_0074 years ago
Occasional Contributor
I was tried to debug program. So funtion alt_32 data = IORD(&pmac->mdio0.CONTROL, ALTERA_TSE_PCS_IF_MODE); was not working. /* @Function Description: Configure operating mode of Altera PCS if available * @API Type: Internal * @param pmac_info pointer to MAC info variable * @return return SUCCESS */ alt_32 alt_tse_phy_cfg_pcs(alt_tse_mac_info *pmac_info) { alt_tse_system_info *psys = pmac_info->psys_info; np_tse_mac *pmac = (np_tse_mac *) psys->tse_mac_base; alt_tse_mac_group *pmac_group = pmac_info->pmac_group; /* get index of the pointers in pointer array list */ alt_8 mac_info_index = alt_tse_get_mac_info_index(pmac_info); alt_8 mac_group_index = alt_tse_get_mac_group_index(pmac_group); if(psys->tse_pcs_ena) { tse_dprintf(5, "INFO : PCS[%d.%d] - Configuring PCS operating mode\n", mac_group_index, mac_info_index); alt_32 data = IORD(&pmac->mdio0.CONTROL, ALTERA_TSE_PCS_IF_MODE); // Program stop debug at here if(psys->tse_pcs_sgmii) { tse_dprintf(5, "INFO : PCS[%d.%d] - PCS SGMII mode enabled\n", mac_group_index, mac_info_index); IOWR(&pmac->mdio0.CONTROL, ALTERA_TSE_PCS_IF_MODE, data | 0x03); } else { tse_dprintf(5, "INFO : PCS[%d.%d] - PCS SGMII mode disabled\n", mac_group_index, mac_info_index); IOWR(&pmac->mdio0.CONTROL, ALTERA_TSE_PCS_IF_MODE, data & ~0x03); } } return SUCCESS; } Can you tell me a solution to this problem? Thank!- EngWei_O_Intel4 years ago
Frequent Contributor
Hi
Are you saying you no longer having compilation issue and the issue now is on the TSE IP? Pin planner and assignment editor should generate the same outcomes if the changes made is regarding to pin location.
Thanks.
Eng Wei
- EngWei_O_Intel4 years ago
Frequent Contributor
Hi there
We do not receive any response from you to the previous reply that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Eng Wei