Forum Discussion
Altera_Forum
Honored Contributor
16 years agoYour process that generates the clock is also triggered by the clock, which won't work. It's a bit like the chicken-and-egg problem ;)
You should have two processes, one to generate the clock, and another one that triggers on it: Clockgen: process
begin
clock <= not clock after 10 ns; --will give 50MHz clock
end process;
Sim: process (clock)
begin
if rising_edge(clock) then
counter_out <= counter_out + 1;
end if;
end process;It is also a good idea to add a reset signal to give your counter (and clock) an initial value. If you don't do that counter_out will start with UUUUU (uninitialised) in the simulator and will become XXXXX (unknown) at the first clock cycle.