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dfowlkes's avatar
dfowlkes
Icon for New Contributor rankNew Contributor
4 years ago

MSI PCIE Interrupt set up using Avalon-MM PCIe Hard IP Core as a Qsys component...

I'm confused about how to properly set up MSI interrupts across the PCIe interface using the Avalom-MM interface of the PCie Hard IP Core. I am confident the PCIe host driver is enabling MSI's corre...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


May I know which device you are using? Do you configure the IP as Root port or Native endpoint? You may generate the example design using the IP parameter GUI and refer to the software folder for reference.


Thanks

Best regards,

KhaiY


  • dfowlkes's avatar
    dfowlkes
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hello!

    Yes, I am using a Stratix IV board with FPGA EP4SGX230KF40.

    I'm designing an endpoint not a root port.

    Which example design should I be looking at that shows how to get the MSI working?

    Daryl