Forum Discussion
Occasional ContributorMemory read stall rate
Occasional ContributorI am able to achieve frequency of 230 MHz( on Arria 10) , also I have like that access and writing of the result, I believe having reading and writing port should have not result in memory contention. Is my assumption correct.
Also , I am able to achieve high memory bandwidth (with high occupancy) when I am reading, but for writing output memory( with low occupancy) is very low , also I am not able to figure out what could be the reason for that. Can you suggest how to improve output writing bandwidth
Frequent ContributorIs this the same code as the one in your other thread? The read access is 512-bit wide which means it can efficiently saturate the bandwidth of one memory bank. However, the write is narrow and unless you have multiple consecutive writes that are coalesced into one wider access, write performance is going to be poor. You should check the HTML report to see how the memory ports are instantiated by the compiler. Since, by default, the compiler interleaves buffers if your board has two memory banks, your reads and writes can actually conflict. But if you disable memory interleaving as mentioned in the Programming Guide and put the input and output buffers on separate memory banks, then the accesses will not conflict with each other.
- ADua0
Yes that is the same code as in my other thread. If I check my board specification, I have only one DDR4 memory bank. I can see in the report generated that multiple ports are generated for the storing the data, as you can see in the attached photo. I thought that even having one memory bank there will be separate read and right ports that means there should not be any memory contention is that not correct.
I am although writing to consecutive write port they are not coalesced , is it correct to say?. If yes then having one like write float8 or float16 and one read of float16 could be the best case given I have one memory bank ?
