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Altera_Forum
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14 years ago

Looking for a design for the Cyclone III FPGA Development Board with MMU

I'm looking for a recent design for the cyclone iii fpga development board using a Nios2 with MMU and the TSE. I am using QII 10.1sp1 and SOPC Builder. Are there some as 'reference design' ? ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The Worst case Timing Paths indicates a slack=-0.033 for the Slow 1200mV 85C Model Setup of the ddr2_Lo_xxx|altpll_component|...pll1|clk[1].

I don't know if there is a relationship, but the verification fails after a nios2-download of my kernel...