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astrocyte's avatar
astrocyte
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4 years ago

Interfacing custom Avalon MM Master with SPI (3 Wire Serial) Intel FPGA IP

I wrote a custom Avalon MM Master Component that interfaces via Qsys interconnect with a SPI (3 Wire Serial) Intel FPGA IP instance. The signals and waveforms specified by the SPI core control por...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
4 years ago

Glad you issue had been solved. I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.