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I think the memory here is for the image data itself, the data from the camera module? So, I have to implement 2 memories. (Correct me if I'm wrong):
1. One to hold the image data from the camera -
this is the ram you were referring to? 2. One to hold the Algorithm bit stream to be loaded to the FPGA for it to be reconfigured to do the processing - I'll use an SD card for this.
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The memory can be for image data, or also your compression algorithm. I'm not sure how you are going to load the algorithm into the FPGA as a bitstream - is it going to be the whole algorithm, or just parameters to the algorithm? I would actually write the algorithm in HDL (means this is part of your SOF), and only load the parameters as a bitstream. However, even with this I would load the bitstream into a RAM (best if internal RAM), so the algorithm doesn't need to access the external SD card all the time at every loop. Imagine, if your algorithm is running, and you remove the SD card, your whole system is going to fail. So, I'd always load the bitstream to (internal or external) RAM.
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So, I'm thinking the process will go like this: (Assuming that the image data from the camera is stored in a memory (RAM))
a. Choose compression option
b. The bit stream from the SD Card is loaded to the FGPA
c. The FPGA is reconfigured to do the compression
d. The RAW data from the RAM is fed through the FPGA (I don't know if this is what really happens)
e. The processed data is stored in the RAM as a compressed image data.
If I'm correct, what part of this process does the scan chain happen?
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You're almost there. This process will start after you have already configured your FPGA using Quartus. The scan chain bitstream scanning will happen in (b), after your FPGA is already configured by Quartus. (c) is also related to (b), where after scanning in the bitstream, your FPGA automatically already gets configured with the new compression algorithm. For (d), usually RAW comes from the image sensor, but u will want to store it once in RAM before you do further processing (such as JPEG compression). The processing should work on the contents of the RAM, and not modify contents in the SD card (if for example, u want to load an image from SD instead of sensor and do image processing on it). For your JPEG compression, it is also better to have the compression parameters stored in RAM, so that your algorithm can use it directly from RAM instead of rely on SD card (again, SD card may be removed anytime during runtime).
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So what do I do to reconfigure? Write THE controller to access the JTAG?
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Reconfigure the FPGA using the normal way, Quartus programmer via USB JTAG. Your design should contain another controller to scan in the bitstream via another interface (maybe another USB port, or others).
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