--- Quote Start ---
You can use the same external SD memory to do your RAW-to-JPEG manipulation, JPEG compression, etc., and use something like a temporary file for the manipulation of bits. But I personally would want to manipulate bits in a RAM (could be on-chip RAM like M4K/M8K, or external RAM) because it performs faster. So it depends on how fast you want your application to work.
--- Quote End ---
I think the memory here is for the image data itself, the data from the camera module? So, I have to implement 2 memories. (Correct me if I'm wrong):
1. One to hold the image data from the camera -
this is the ram you were referring to? 2. One to hold the Algorithm bit stream to be loaded to the FPGA for it to be reconfigured to do the processing - I'll use an SD card for this.
So, I'm thinking the process will go like this: (Assuming that the image data from the camera is stored in a memory (RAM))
a. Choose compression option
b. The bit stream from the SD Card is loaded to the FGPA
c. The FPGA is reconfigured to do the compression
d. The RAW data from the RAM is fed through the FPGA (I don't know if this is what really happens)
e. The processed data is stored in the RAM as a compressed image data.
If I'm correct, what part of this process does the scan chain happen?
I got confused with the memory part because you pointed out that from the SD card, the bit stream must be loaded to an internal memory. I'm assuming now that the bit stream you were referring to here is the image data from the camera not the JPEG algorithm (HDL) bit stream for configuring the FPGA.
I know that a controller must be implemented to handle control and interface with the FPGA, memory, camera, etc. Also, to load the configuration bits from the SD to reconfigure the FPGA. However, from the quote below, the controller I mention here does not do this function (reconfiguring). So what do I do to reconfigure? Write THE controller to access the JTAG?
--- Quote Start ---
No, this is a different controller. Your controller does not reconfigure the whole FPGA the way Quartus configures the FPGA. The built-in JTAG controller in the FPGA does the configuring. Now, you want to implement your own controller that configures a part of your whole design, so you need to write a separate HDL for it (your HDL, again, is not the same as the built-in JTAG configuration controller in the FPGA).
--- Quote End ---
Honored Contributor
