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And what do you mean by "interface to the FPGA"?
Is the interface you mention here the same with the interface in the next quote (RS232/USB/etc.)? If not, what is the interface logic here for?
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Yes, I meant the same interface as in the next quote.
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If HDL code is to be compiled and loaded in the FPGA, how then is the implementation done in NIOS?
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The "implementation" in the FPGA should as much as possible be similar (HDL and Nios), it is just the source files that are different. For HDL, you would use VHDL or Verilog, or other HDL formats, while for Nios, you would use C for the source code. The resulting RTL from both should be similar (though not always so - I still prefer HDL to Nios when improving area/efficiency).
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When the bit stream is scanned why does it have to be stored somewhere? Can't it be loaded to the FPGA immediately? What is the other memory for?
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You can use the same external SD memory to do your RAW-to-JPEG manipulation, JPEG compression, etc., and use something like a temporary file for the manipulation of bits. But I personally would want to manipulate bits in a RAM (could be on-chip RAM like M4K/M8K, or external RAM) because it performs faster. So it depends on how fast you want your application to work.
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Doesn't the controller I'm planning to implement (with HDL or NIOS) handles the reconfiguring? Here, the "configuration controller" pertains to upon power up, not during run time?
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No, this is a different controller. Your controller does not reconfigure the whole FPGA the way Quartus configures the FPGA. The built-in JTAG controller in the FPGA does the configuring. Now, you want to implement your own controller that configures a part of your whole design, so you need to write a separate HDL for it (your HDL, again, is not the same as the built-in JTAG configuration controller in the FPGA).
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Can this configuration controller be used as the reconfiguration controller during run time to load in the new scanned bit stream instead of the one discussed above?
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Yes. But only to load the new bitstream for your JPEG compression/or whatever other function. You can't use this to configure the whole FPGA (i.e. you can't load a SOF/POF with this).
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Please bear with me:) Thank you very much.
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No problem.
Honored Contributor
