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okay, my guess was something like that too... :) You can write a controller in HDL to do those things.
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So I can implement the controller in a portion of the FPGA chip OR I can use the NIOS right? If I go for the first one then I would have to retain the circuitry of the controller while reconfiguring the other portion for the image processing. If I go for the NIOS then I would have to implement an interface to the FGPA. Which do you suggest?:)
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you very well need the shift register / scan chain logic then...
Yes, you're right. It probably would be just some shift registers, or some kind of matrix memory controlled by some logic. You might even like to write your HDL such that it uses the internal RAM (such as M4K, etc.) of the device. Well, you can write your own flavour using your own taste... :)
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Either choice of controller implementation I would have to use scan chain logic right? What would the memory be used for? I get the concept of scanning in bit stream to configure but I don't get why use a memory/shift register/RAM. Can't I use the controller to read the configuration bits from an external memory like an SD card and just load it to the FPGA? Is the memory you're referring to a memory that is holding the reconfiguration bits of the compression algorithm?
Oh yeah! regarding the reconfiguration of the FGPA, my HDL code would be compiled into a bit stream that would configure the chip right? I am in the assumption that I would always need the Quartus software to configure the chip. If that's the case then how can the chip be changed without the software?:)
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