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The controller would be for:
1. Yes, handling commands such as "capture image", "store to sd card", "display on lcd", compress to <compression type>". For the compression type I would implement JPEG but the project leaves room for future developments of other compression types.
2. It would also serve as the configuring device during run time. The idea is when the "compress <>" option is chosen, the corresponding synthesized HDL code of the compression would be loaded to the portion of the FPGA to be reconfigured. The reconfiguring bit stream (compression HDL code) would come from a memory (SD Card for example) and loaded by the controller (NIOS or FPGA implementation) to the FPGA compression portion.
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okay, my guess was something like that too... :) You can write a controller in HDL to do those things.
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I will implement the compression in Verilog but I need the capability to load it at run time so that future compression algorithms could be added during run time (as users need them).
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you very well need the shift register / scan chain logic then...
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From what I understand about the scan chain, it looks like the concept of using a controller to load the compression algorithm bit stream to reconfigure the fpga. Am I correct?
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Yes, you're right. It probably would be just some shift registers, or some kind of matrix memory controlled by some logic. You might even like to write your HDL such that it uses the internal RAM (such as M4K, etc.) of the device. Well, you can write your own flavour using your own taste... :)
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