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What is this controller for? I am guessing that this controller receives user inputs and processes those inputs.
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The controller would be for:
1. Yes, handling commands such as "capture image", "store to sd card", "display on lcd", compress to <compression type>". For the compression type I would implement JPEG but the project leaves room for future developments of other compression types.
2. It would also serve as the configuring device during run time. The idea is when the "compress <>" option is chosen, the corresponding synthesized HDL code of the compression would be loaded to the portion of the FPGA to be reconfigured. The reconfiguring bit stream (compression HDL code) would come from a memory (SD Card for example) and loaded by the controller (NIOS or FPGA implementation) to the FPGA compression portion.
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7. I am thinking that you should put the JPEG compression algorithm in the HDL, which means it becomes active as soon as your machine becomes active.
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I will implement the compression in Verilog but I need the capability to load it at run time so that future compression algorithms could be added during run time (as users need them).
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But if you really need to load this algorithm everytime you do a JPEG compression, then you can write your own scan chain (see below).
Or, what I'd do is write my own scan chain and have it hooked to an interface to receive data.
you can scan in the new algorithm into your FPGA using the said interface + scan chain. The scan chain could be just some shift registers, or controls to internal/external memory.
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From what I understand about the scan chain, it looks like the concept of using a controller to load the compression algorithm bit stream to reconfigure the fpga. Am I correct?
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