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1. Capture an image
2. Display the Image on the LCD
3. Store the Image in an SD card
4. Convert the image into a JPEG format.
5. Have a user interface to control these functions.
6. The user interface should be implemented on top of a controller
7. The controller should load the JPEG algorithm bit stream into the FPGA to configure it at runtime from a memory (like the SD card).
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1. I don't have a DE2 board with me, so I don't know exactly how to do this. But, you can take a look at the CMOS imager specs and write your HDL based on it. It's basically just handshaking between the FPGA and this CMOS imager, and getting all the data correctly.
2/3. Again, take a look at the LCD's specs. For the SD card, you need to implement the SDIO interface in the FPGA. Think there are a few free implementations on this out there...
4. Haven't done JPEG, sorry...
5. Not sure if the LCD panel is also a touchscreen? If so, you can write HDL that renders the UI graphics to the touchscreen. Just superimpose the UI on top of the image that's currently on the screen. Or, you can play around with alpha-blending.
6. What is this controller for? I am guessing that this controller receives user inputs and processes those inputs. If so, for a simple touchscreen controller, just detect the coordinates of a user "touch". Be sure to add at least a few adjacent pixels to be certain it is the user who "touched" the screen, rather than some bug or dust.
7. I am thinking that you should put the JPEG compression algorithm in the HDL, which means it becomes active as soon as your machine becomes active. But if you really need to load this algorithm everytime you do a JPEG compression, then you can write your own scan chain (see below).
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In reconfiguring the Cyclone II, does the whole chip need to be altered? or can only a portion of it alloted for JPEG compression be changed? I ask this because I plan to implement the controller in the FPGA chip instead of the NIOS II embedded controller.
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No, you don't need to reconfigure the whole chip. You can try the "partial reconfiguration" feature released by Altera a while ago, though I've never tried it yet. Or, what I'd do is write my own scan chain and have it hooked to an interface to receive data. The interface can be USB/Ethernet/Wi-Fi or whatever. For example, say you've made changes to your JPEG compression algorithm and you want your FPGA to reload the new algorithm, then you can scan in the new algorithm into your FPGA using the said interface + scan chain. The scan chain could be just some shift registers, or controls to internal/external memory. What the scan chain does is just receive data from the interface, and stores the data accordingly (usually in shift registers, but can be other internal/external memory as well). This would update your old algorithm with the new data given by the user. You could also implement your own protocols for storage/memory control or error detection in between the interface controller and the scan chain (if you wish).
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