huge delay inserted by Quartus 19.3 pro on the Arria 10 FPGA

Hi sstrell,

I tested with global clock usage and that solves the mess for that clock.

But then on the next clock gating that follows that clock there are again extra 3 ns extra delay.

For some reason the Quartus 13.1 and/or stratix III was handling the clock gating much better than with quartus 19.3 and/or the Arria 10.

Our design has definition for about 200 clocks and have thousands of clock gating (low power).

Attaching a picture of the next long routing for the next clock gate after the global clock point.