huge delay inserted by Quartus 19.3 pro on the Arria 10 FPGA

For example, the following path (gated clock block output to FF):

rfd_ic_i|u_top|u_core|u_rfd_clockshop|i_mcu_flexcomm1_clockgate|i01_cnhlspd|Q -> rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array_1__A_flexcomm|genblk1_A_flexcomm|A_flexcomm_ctrl_gen_A_flexcomm_ctrl|A_flexcomm_fifo|A_flexcomm_fifo_ptrs_rx|rptr_gray_0_

takes 0.68 ns in quartus 13.1 stratix 3

and takes 9.1 ns !!! in quartus 19.3 Arria 10.

Why is quartus adding so much delay in that path for the arria 10?

Attaching 4 pictures showing this.

report command was:

report_timing -from_clock { flexcomm1_hclk } -to_clock { flexcomm1_hclk } -from {rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array_1__A_flexcomm|genblk1_A_flexcomm|A_flexcomm_ctrl_gen_A_flexcomm_ctrl|A_flexcomm_fifo|A_flexcomm_fifo_ptrs_rx|rptr_0_} -to {rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array_1__A_flexcomm|genblk1_A_flexcomm|A_flexcomm_ctrl_gen_A_flexcomm_ctrl|A_flexcomm_fifo|A_flexcomm_fifo_ptrs_rx|rptr_gray_0_} -hold -npaths 100 -detail full_path -panel_name {Report Timing}