how to store binary bit sequence in Stratix V GX Signal Integrity kit FPGA memory and transmit throu

Hi,

As I understand it, this seems to be similar to another thread of yours at https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Storing-bitstream-in-Startix-V-GS-SI-eval-kit-and-transmitting/m-p/1278214#M19829. To facilitate the tracking, this thread will be transitioned to community support. We shall continue to follow up with you on the other thread.

Thank you.