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WKUAN's avatar
WKUAN
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4 years ago

How to instaniate a SFL ip core in the design

Hello, I am using ARRIA10 with EPCQL1024, now the ARRIA10 is ok, the SOF can be configured into the FPGA, but when I configure the EPCQ1024 with JIC file, the configuration failed. After read an...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Kuang Wu,


This is confusing. But by right you will be able to select the appropriate device ordering number in signal tab after the JTAG is ready.


Thank You


WKUAN's avatar
WKUAN
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4 years ago

Hi Bruce，

Error (12852): Data integrity error is detected during JTAG communication. The SignalTap result is not trustworthy. Please check the JTAG chain.

this is the echo of quartus.

Thank you