Forum Discussion

WKUAN's avatar
WKUAN
Icon for New Contributor rankNew Contributor
5 years ago

How to instaniate a SFL ip core in the design

Hello, I am using ARRIA10 with EPCQL1024, now the ARRIA10 is ok, the SOF can be configured into the FPGA, but when I configure the EPCQ1024 with JIC file, the configuration failed. After read an...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


You dont need to instantiate SFL IP when you are programming JIC into FLASH using Quartus Programmer.


May i know what error you got during programming?


Regards,

Bruce


  • WKUAN's avatar
    WKUAN
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi Bruce,

    Thank you.

    I am afraid the EPCQL1024 chip is damaged, because i can not configure the chip.

    Now I have a new problem, the FPGA on my board is 10AX115N3F45E2, but when I scan chain in signaltap, the chip is 10AT115S1, so i can not debug the chip with signaltap. when i use programmer with the .sof file, it is ok to configure the chip 10AX115N3F45E2, and the code works, it is very confusing!

    KUANG Wu